COMPARATOR


AIM:Design and implement a 4bit comparator.

DESIGN
COMPARATOR
Verilog Program- Comparator

`timescale 1ns / 1ps

///////////////////////////////////////////////////////////////////////////
// Company: TMP
// Create Date: 08:15:45 01/12/2015
// Module Name: Comparator
// Project Name: Comparator
///////////////////////////////////////////////////////////////////////////
module Comparator(A,B,gt,lt,eq);
input [3:0] A,B;
output reg gt,lt,eq;

always @(A,B)
begin
if(A>B)
begin
gt=1;
eq=0;
lt=0;
end
else if(A < B)
begin
gt=0;
eq=0;
lt=1;
end
else
begin
gt=0;
eq=1;
lt=0;
end
end
endmodule

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