`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: // // Create Date: 09:07:55 05/01/2015 // Design Name: // Module Name: UpDownCounter // Project Name: // Target Devices: // Tool versions: // Description: // // Dependencies: // // Revision: // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// module UpDownCounter(clk,enable,reset,mode,count,tc); input clk,enable,reset,mode; output reg [7:0]count; output reg tc; always @(posedge clk) begin if(enable) begin if(reset) begin count=0; tc=0; end else begin if(mode==0) begin count=count+1; if(count==255) tc=1; else tc=0; end else begin count=count-1; if(count==0) tc=1; else tc=0; end end end end endmodule