- Basic Logic Gates
- Half Adder
- Full Adder
- Verilog program for 4bit Adder
- Half Substractor
- Full Substractor
- 4bit Substractor
- Carry Look Ahead Adder
- 3:8 Decoder
- 8:3 Encoder
- 1:8 Demultiplxer
- 8:1 Multiplexer
- 8bit D Flipflop
- T Flipflop
- JK Flipflop
- 8bit Up/Down Counter
- Shift Register
- Sequence Detector(Moore)
- Sequence Detector(Mealy)
- Programmable Clock Generator
There are different ways to add delay in ARM controller. One of the simplest way to add delay is to use an empty for loop. The loop executes as many times as the count value specified. But this kind of delay is not precise. For precise timing applications, we use timers. LPC1769 comes loaded with four 32 bit general purpose timers. Each Timer can be used as a ‘Timer’ or as a ‘Counter’ and can be also used to demodulate PWM signals given as input.
A timer has a Timer Counter (TC) and Prescale Register(PR) associated with it. When Timer is reset and Enabled TC is set to 0 and incremented by 1 every ‘PR+1′ clock cycles. When it reaches its maximum value it gets reset to 0 and hence restarts counting. Prescale Register is used to set the count resolution of the timer. If PR=0 then TC is incremented every 1 clock cycle of the peripheral clock. If PR=1 then TC is incremented every 2 clock cycles of peripheral clock and so on.MATCH REGISTER(MR)
A Match Register is a Register which contains a specific value set by the user. When the Timer starts – TC incremented every PR+1 clock cycles. If it matches with the count value stored in match register, it can reset the timer or can generate an interrupt as defined by the user.
Match Registers can be configured to: • Stop Timer on Match and trigger an optional interrupt. • Reset Timer on Match and trigger an optional interrupt. • To count continuously and trigger an interrupt on match.
Capture register is used to Capture Input signal. When a transition event occurs on a Capture pin, it can be used to copy the value of TC into any of the 4 Capture Register or to generate an Interrupt.
The Timer 0, 1, 2, and 3 peripherals are configured using the following registers:
1. Power: In the PCONP register, set bits PCTIM0/1/2/3. On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled (PCTIM2/3 = 0).
2. Peripheral clock: In the PCLKSEL0 register, select PCLK_TIMER0/1; in the PCLKSEL1 register, select PCLK_TIMER2/3.
3. Pins: Select timer pins through the PINSEL registers. Select the pin modes for the port pins with timer functions through the PINMODE registers.
4. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
5. DMA: Up to two match conditions can be used to generate timed DMA requests.
Registers used for ADC programming in LPC17xx:Count Control Register (CTCR)
Interrupt Register (IR)
The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be high. Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match also clears any corresponding DMA request.
Timer Control Register (TCR)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter. Bit0 is used to enable the timer and Bit1 is used to reset the timer.
The Count Control Register (CTCR) is used to select between Timer and Counter mode and in Counter mode to select the pin and edge(s) for counting. When Counter Mode is chosen as a mode of operation, the CAP input (selected by the CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two consecutive samples of this CAP input, one of the following four events is recognized: rising edge, falling edge, either of edges or no changes in the level of the selected CAP input. Only if the identified event occurs and the event corresponds to the one selected by bits 1:0 in the CTCR register, will the Timer Counter register be incremented. Bit[1:0] decides the mode of operation.
00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register. The Prescale counter is incremented on every rising PCLK edge.Timer Counter registers (TC)
01 Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
10 Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
11 Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.
The 32-bit Timer Counter register is incremented when the prescale counter reaches its terminal count. Unless it is reset before reaching its upper limit, the Timer Counter will count up through the value 0xFFFF FFFF and then wrap back to the value 0x0000 0000. This event does not cause an interrupt, but a match register can be used to detect an overflow if needed.
Prescale register (PR)
The 32-bit Prescale register specifies the maximum value for the Prescale Counter.
Prescale Counter register (PC)
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter. This allows control of the relationship of the resolution of the timer versus the maximum time before the timer overflows. The Prescale Counter is incremented on every PCLK. When it reaches the value stored in the Prescale register, the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK. This causes the Timer Counter to increment on every PCLK when PR = 0, every 2 pclks when PR = 1, etc.
Match Registers (MR0 - MR3)
The Match register values are continuously compared to the Timer Counter value. When the two values are equal, actions can be triggered automatically. The action possibilities are to generate an interrupt, reset the Timer Counter, or stop the timer. Actions are controlled by the settings in the MCR register.
Match Control Register (MCR)
The Match Control Register is used to control what operations are performed when one of the Match Registers matches the Timer Counter.
Configuring a Timer
Now let’s see how to configure and setup a timer.
1. Reset the timer by configuring TCR. 2. Set Prescale value in PR 3. Set the count value in Match register(MR) 4. Set appropriate value in MCR. 5. Enable the timer by configuring TCR. 6. Enable timer interrupt if needed.
LPC_TIM0->TCR = 0x02; /* reset timer */Our next tutorial is about generating a square wave by configuring the timer interrupt. programmable pulse generator using LPC17xx (LPC1769
LPC_TIM0->PR = 0x00; /* set prescaler to zero */
LPC_TIM0->MR0 = 2400; /* set the count value */
LPC_TIM0->IR = 0xff; /* reset all interrupts */
LPC_TIM0->MCR = 0x04; /* stop timer on match */
LPC_TIM0->TCR = 0x01; /* start the timer */
LPC176x/5x General Purpose Input/Output (GPIO) Programming
LPC176x/5x Timer Programming
LPC176x/5x Analog-to-Digital Converter (ADC)
Square Wave Generator using LPC17xx (LPC175x/LPC176x/LPC1769)
Sine Wave Generator using DAC with LPC17xx (LPC175x/LPC176x/LPC1769)