Design and implement an 8bit d-flipflop with enable input and synchronous clear.
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: EAM
// Create Date: 08:15:45 04/29/2015
// Module Name: 8bit DFlipflop
// Project Name: 8bit DFlipflop
//////////////////////////////////////////////////////////////////////////////////
module DFlipflop(Din,clk,clear,enable,Q);
input [7:0]Din;
input clk,clear,enable;
output reg [7:0] Q;
always@(posedge clk)
if(enable)
begin
if(clear)
Q<=0;
else
Q<=Din;
end
endmodule